Vertical Compressive Stress in Fab-Integrated WS2 FETs: An In Situ Electrical and Nanoindentation-Based Study

Abstract

Abstract Two-dimensional (2D) semiconductors are sensitive to mechanical stress due to their atomic thickness, weak van der Waals interfaces, and ultra-high sensitivity to the surrounding dielectric environment. While the effects of in-plane strain in transition-metal dichalcogenides (TMDs) have been extensively studied, the influence of locally generated out-of-plane compressive stress—commonly introduced during fabrication, packaging, and 3D integration—remains largely unexplored. Here, we apply controlled GPa-level perpendicular stress to monolayer WS2 field-effect transistors (FETs) using a nanoindenter integrated with in situ electrical measurements. Vertical compression reduces the on-state current by up to ∼74.2%, with partial recovery after unloading. Finite element modeling and electro-mechanical TCAD simulations indicate that mobility degradation is dominated by stress-induced enhancement of WS2–oxide interfacial coupling rather than intrinsic band-structure modification. Photoluminescence and Raman spectroscopy reveal that the WS2 lattice remains intact and show ∼0.5% relaxation of intrinsic tensile strain. These results establish a quantitative framework for understanding vertical-stress-driven transport degradation and highlight out-of-plane compression as an emerging reliability challenge for 2D materials in future stacked and heterogeneous device architectures.