A 128−Channel 0.2–8.2 V Calibrated DAC IC Achieving 0.26−LSB DNL and 0.71−LSB DVO for Photonic Computing

Abstract

Photonic computing systems require large numbers of accurate programmable voltages for photonic weight programming and device bias control. This paper presents a 128−channel digital−to−analog converter (DAC) implemented in a 250 nm BCD high−voltage CMOS process. A code−dependent per−channel auxiliary−DAC calibration scheme is proposed to compensate main−DAC conversion errors and channel−dependent offsets. In addition, a separated low−/high−voltage−domain driver and a stepwise multichannel update scheme are adopted to reduce static power and suppress update−induced disturbances. After calibration, the measured maximum absolute differential non−linearity (DNL) and integral non−linearity (INL) are 0.26 least significant bit (LSB) and 0.39 LSB, respectively, and the maximum deviation of voltage output (DVO) across 128 channels is 0.71 LSB. The DAC achieves rising/falling slew rates of 6.1/11.7 V/μs under an 8 V output swing. Under dynamic operation with 0.2 to 8.2 V sinusoidal outputs and a 10 kΩ load per channel, the total power consumption is 0.85 W. Thermo−optic phase−shifter measurements further verify programmable photonic phase tuning, demonstrating a scalable electrical control interface for thermo−optic phase−shifter−based photonic computing hardware.