Impact of Source Contact Segmentation on the Electrical Characteristics of 4H‐SiC Planar MOSFETs

Abstract

Source contact (SC) segmentation is investigated as a layout approach for tuning the capacitance, conduction, blocking, and switching characteristics of 1.7 kV 4H‐silicon carbide (4H‐SiC) planar metal‐oxide‐semiconductor field‐effect transistors (MOSFETs). Three‐dimensional TCAD simulations and measurements of fabricated small and large area devices show that SC segmentation reduces the input capacitance ( C iss ) primarily through a decrease in the gate–source capacitance ( C gs ), while the gate–drain capacitance ( C gd ) and output capacitance ( C oss ) remain nearly unchanged. In the small area devices, C iss and the leakage current at 1700 V decreased by 1.04%–4.66% and 62.3%–89.4%, respectively, whereas the specific on‐resistance ( R on,sp ) and third‐quadrant forward voltage ( V F ) increased by 5.77%–11.54% and 16.0%–20.8%. Consequently, the high‐frequency figure‐of‐merit (HF‐FOM) increased by 6.5%–11.5%. The large area SC (1:2) device exhibited a more balanced trade‐off, with reductions of 1.53%, 1.54%, and 61.8% in C iss , C gs , and leakage current, respectively, while R on,sp and HF‐FOM increased by only 1.94% and 0.7%. Double pulse test (DPT) measurements further showed reductions of 5.41% in total switching energy. The gate‐source leakage current ( I GSS ) and overall gate charge ( Q G ) characteristics remained nearly unchanged. These results demonstrate that moderate SC segmentation can reduce C gs , leakage current, and switching energy while maintaining a limited conduction penalty.