Charge‐Domain In‐Memory Computing With NAND‐Compatible Ferroelectric Memcapacitor Crossbar

Abstract

ABSTRACT Rapid growth in artificial intelligence has intensified the need for energy‐efficient computing architectures beyond the conventional von Neumann paradigm. While memristive in‐memory computing has attracted significant attention, its low cell resistance causes static power consumption, IR‐drop‐induced errors, and scalability limitations. Here, we demonstrate a NAND‐compatible ferroelectric memcapacitor crossbar for scalable and energy‐efficient in‐memory computing. The proposed architecture employs charge‐domain operation with intrinsically high cell resistance, strongly suppressing static conduction and reducing energy consumption. Optimized device design enables a large charge memory window, reliable multilevel storage, and non‐destructive readout. Experimental vector–matrix multiplication (VMM) exhibits highly linear behavior due to displacement‐current‐based computation, which alleviates IR‐drop effects. Circuit‐level validation confirms practical sensing feasibility, while parasitic‐aware SPICE simulations based on a 3D NAND architecture verify robust operation under deeply stacked conditions. Finally, CIFAR‐10 image classification and spiking neural network inference highlight the strong potential of ferroelectric memcapacitor arrays as a scalable platform for energy‐efficient neuromorphic and in‐memory computing applications.