Channel decoupling of the memory window in CuInP2S6-gated two-dimensional ferroelectric transistors: conditions, limits, and implications for interface processing

Abstract

We ask which properties of the channel can change the memory window of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) ferroelectric transistor gated by CuInP 2 S 6 . For a window read at a constant drain current we derive a conditional expression: if the floating gate is an equipotential plane, the ferroelectric carries no charge other than its polarization, and the drain current is the same function of the channel state on both branches of the loop, then the read fixes the channel carrier density at threshold, the surface potential and free channel charge cancel between branches, and the window depends only on the ferroelectric thickness, the switched polarization at the two threshold crossings, and the trapped interface charge. We test it against a simulation of a CuInP 2 S 6 /h-BN/ WSe 2 device in which biaxial strain changes the hole mobility 26-fold; the two agree to within 0.02 percent on a fine sweep grid, and we give closed-form corrections for branch-dependent mobility, unequal capacitor areas, and charge on the ferroelectric side. The channel is not removed from the physics: it enters through the switched polarization, which at threshold is set by the depolarization field and during programming by the charge the stack can supply. The window is therefore channel insensitive only when the channel quantum capacitance at the program extreme exceeds the interlayer capacitance by about tenfold and the read level lies below the onset of switching. Within these conditions the model predicts that compressive strain raises the retained read current 1.90 times without changing the window, and that interface trapping is the channel-side process that limits it. We propose a single-run experiment that can falsify these predictions.