A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology

Abstract

Abstract This work introduces a fully tunable, ultra-low power unipolar memory cell inspired by the Schmitt-trigger comparator and designed in CMOS using only nine transistors. The proposed circuit operates entirely in the current domain and exploits a novel feedback configuration between two interdependent Heaviside-like thresholding elements to produce tunable bistable switching behavior. Its three key parameters—threshold current, hysteresis width, and output gain—are independently tunable via programmable bias currents, enabling flexibility across diverse analog computing applications. Unlike prior Schmitt-trigger designs, it simultaneously achieves current-mode operation, nanowatt-range power consumption, and full tunability, solely using standard MOSFET elements. Schematic-level and post-layout simulations in a 180 nm CMOS process confirm robust hysteresis together with resilience to device mismatch, supply variation, and process variation, while the residual temperature drift of the switching thresholds can be compensated through a PTAT-based bias reference. The operating current additionally sets a predictable trade-off between bandwidth and power consumption. Building on this circuit, we develop a complete family of spike-based logic gates using three-level current encoding, where the bistable memory retains the polarity of the last spike on each input indefinitely, enabling asynchronous logic operations without temporal windowing or refresh mechanisms. The same circuit also serves as the primitive for Bistable Memory Recurrent Units in analog neural networks, where the quantized hidden states provide inherent noise immunity. Together, these capabilities position the design as a versatile building block for next-generation neuromorphic processors integrating memory, logic, and recurrent computation.