Monolithic Intrinsic-Capacitance Bootstrapped Inverter in E-Mode GaN-on-SOI: Design, Analysis, and Electro-Thermal Characterization

Abstract

This paper presents, analyzes, and experimentally validates a bootstrapped inverter implemented via low-voltage enhancement-mode HEMTs offered by a 200-V E-mode GaN-on-SOI monolithic platform. Unlike conventional resistor–transistor logic (RTL), the proposed topology exploits intrinsic device capacitances to achieve a transient current-source-like pull-up behavior without dedicated bootstrap capacitors. A detailed analytical model is developed to describe the dynamic operation and to identify the conditions under which the low-to-high transition overcomes the RC limitation of RTL inverters. Measurements demonstrate a more than 30% reduction in rise time, higher static gain, and an overall improvement in total noise margins under comparable static current conditions. The temperature dependence of bootstrap efficiency from −40 °C to 150 °C is also investigated. By combining experimental measurements with model-based parameter extraction, we show that the high-temperature performance crossover is attributed primarily to leakage-induced overdrive reduction. In contrast, threshold-voltage drift acts in the opposite direction and mobility degradation affects both topologies similarly.