Parametric sensitivity and variability-aware evaluation of CNTFET Full adders for robust nanoelectronic design

Abstract

Abstract Carbon nanotube field-effect transistors (CNTFETs) offer a promising pathway beyond silicon complementary metal oxide semiconductor (CMOS), yet comprehensive circuit-level evaluations addressing statistical process variability and system-level validation remain scarce. This study presents a rigorous, multi-dimensional benchmarking of eleven full adder topologies—five CNTFET-native and six CMOS-derived—implemented uniformly in a 32 nm CNTFET technology node using the Stanford Verilog-A compact model. We systematically evaluate nominal performance, supply voltage scaling (0.7–1.1 V), frequency operation (100–400 MHz), chiral vector tuning from (16,0) to (19,0), and static leakage across all eight input combinations. Monte Carlo simulations (200 iterations, ± 10% parameter variation) quantify statistical yield, revealing that simplified approximate architectures achieve near-perfect robustness (98–100% yield), while transmission-gate designs balance energy efficiency and process resilience. Notably, Chew’s 17-transistor adder emerges as the optimal ultra-low-power archetype, achieving a power-delay product of 0.081 aJ, 82% statistical yield, and 3.2× lower system power in a 4:2 compressor application. These findings establish actionable, variability-aware design guidelines for CNTFET-based arithmetic units, bridging the gap between device physics and practical nanoelectronic deployment.