Defect‐Control Strategies for III–V Heteroepitaxy on Silicon

Abstract

In silicon photonics, the direct heteroepitaxy of III–V materials on Si is a highly promising route toward on‐chip integration of high‐density active optoelectronic devices. However, an inherent conflict persists between the high threading dislocation density (TDD) created by lattice mismatch and the stringent requirements for low‐defect densities in high‐performance devices. This conflict is further exacerbated by thermal mismatch stress and the limited epitaxial thickness, which collectively narrow the window for viable solutions. This review systematically examines and compares three classes of defect‑control strategies that span a range of interfacial interaction strengths: bulk endogenous strain engineering, mesoscopic geometric confinement, and interface decoupling. By mapping out these approaches, this review offers a directional framework for selecting low‑defect epitaxial strategies under given constraints on thickness, thermal budget, and integration scheme.