A Ku/K-Band Phase-Locked Frequency Synthesizer with Hz-Level Step and Low Phase Noise Based on DDS and Comb-Spectrum Multiplication

Abstract

Conventional phase-locked loop (PLL) frequency synthesizers face an inherent trade-off between achieving fine frequency stepping and maintaining low phase noise, which restricts the development of high-performance frequency synthesizers in high-frequency bands. To address this issue, this paper proposes and implements a novel Ku/K-band phase-locked frequency synthesizer based on a three-stage architecture, which innovatively combines the high-frequency resolution of direct digital synthesis (DDS) with the low phase noise advantage of comb-spectrum multiplication. In this scheme, a DDS reference module generates a finely tunable reference signal, and a main–sub mixing PLL architecture is constructed: the main loop generates the local oscillator (LO) signal, while the sub loop employs a two-stage comb-spectrum multiplication technique to produce a low-phase-noise radio frequency (RF) signal; the two signals are then mixed to generate an intermediate frequency (IF) signal for feedback phase locking. Measured results demonstrate that the proposed frequency source achieves Hz level frequency stepping over the 16–20 GHz range, with phase noise better than −109 dBc/Hz at 1 kHz offset across the entire band and an optimum value of −109.6 dBc/Hz, while spurious suppression exceeds 85 dBc. Moreover, by leveraging 3D system-in-package (3D-SiP) technology, each module features a miniaturized form factor. These results validate the feasibility of the proposed three-stage mixing PLL architecture in effectively balancing broadband coverage, fine stepping, low phase noise, and low spurious levels, thereby providing a viable technical pathway for the engineering implementation of high-performance frequency synthesizers at high-frequency bands.