JANUS: A Spatial Residue Number System Photonic AI Architecture with Non-Volatile Phase-Change Routing

Abstract

Conventional optical AI processors encode numbers in continuous analog amplitudes (Mach-Zehnder Interferometers / MZIs), accumulating optical power across analog meshes. For a 128x128 matrix multiplication, unreduced analog accumulation requires an unattainable 138.4 dB analog SNR and continuous milliwatt thermal tuning that consumes kilowatts of static hold power. Project JANUS presents a constraint-aware, bounded-exact optoelectronic tensor computing architecture engineered for high-throughput, low-power deep learning acceleration. JANUS eliminates the analog optical bottleneck by replacing continuous amplitude accumulation with:1. Spatial One-Hot Residue Number System (RNS) encoding across discrete waveguides.2. Sub-bandgap non-volatile Sb₂S₃/Sb₂Se₃ phase-change material (PCM) routing with 0 W static hold power.3. Receiverless Ge/Si SAC²M avalanche photodiodes (APDs) driving clocked StrongARM dynamic latches (~100 aJ/op sensing).4. A 65nm GPU-style SIMD CMOS digital backend with a Dual-LUT Cross-Term Engine, compressing on-chip SRAM from 36 GB to 1.5 MB with 0 ppm error. Operating at 100 GHz optical wave-pipelining, JANUS delivers exact INT64 deterministic precision with a verified energy efficiency of 112.8 TMAC/s/W (159.7x higher efficiency than NVIDIA H100 SXM5). Version 3 Release: Added complete 65nm SIMD CMOS digital backend architecture specification (JANUS_Mini16_CMOS_Architecture.pdf) and 5-tier multi-physics co-simulation sign-off report (JANUS_Mini16_Simulation_Report.pdf). Patent Application Reference: Indian Patent Application No. 202611052791 (Patent Pending).Live Platform & Interactive Models: https://janus-photonic-hardware.vercel.app