Hardware-Aware Dynamic Bit-Reordering: Zero-Allocation In-Register Decompression for Analytical Engines

Abstract

In-memory analytical processing (IMAP) engines face severe performance bottlenecks driven by memory bandwidth saturation and cache pollution. Traditional data compression algorithms mitigate memory consumption but introduce significant CPU overhead through heap allocations, cache invalidation, and multi-pass decompression loops. This paper presents DBR-ME (Dynamic Bit-Reorder Memory Engine), a hardware-aware, zero-allocation micro-kernel utilizing x86-64 BMI2 (PEXT/PDEP) and SIMD instruction sets. DBR-ME eliminates static bit-packing constraints by profiling bitwise invariance across 64-byte aligned block structures. Empirical evaluation across 1,000,000 elements demonstrates a sequential vector processing latency of 1.1815 ms under OpenMP multi-threading, an instruction-level zero-spill single-core boundary of 2.1110 ms, and arbitrary random-access record extraction (O(1) read) within 33 ns per element without expanding surrounding block data.