A novel FPGA-based garbled circuit accelerator for secure two-party multiplication (GCMult)

Abstract

Privacy-preserving function execution is crucial for applications such as cloud-based machine learning and IoT. While garbled circuits offer a viable solution, they suffer from high computational and communication costs. Multiplication, a fundamental operation in computing, plays a critical role in overall efficiency. Although parallel execution of independent operations has been widely explored, no prior work has investigated the decomposition of a single multiplication operation into smaller concurrent sub-operations within the garbled circuit framework. This paper introduces GCMult (Garbled Circuit Multiplier), a novel accelerator for garbling secure two-party multiplication that leverages a parallelized decomposition technique for Boolean circuits. Our method applies the Karatsuba algorithm to enhance concurrency while significantly reducing the number of gates, particularly high-cost AND gates. The proposed technique enables a specialized accelerator for garbling multiplication circuits, delivering substantial improvements in both computational speed and communication efficiency. FPGA-based experimental results demonstrate an average 258% reduction in garbling time and more than a 60% improvement in communication bandwidth on average compared to the best existing hardware accelerator. Additionally, our approach achieves a 4140% speedup over the fastest known software implementation, showcasing its potential for scalable and efficient privacy-preserving computations.