A Defect-Tolerant Nano-Manufacturing Framework Toward Low-CapEx Functional Computing: Integrating Nanoimprint Lithography, Directed Self-Assembly, and Hardware–Software Co-Design

Abstract

This preprint presents a cross-layer framework for defect-tolerant nanoscale computing based on NIL–DSA-enabled fabrication, 1S1R memristive crossbar arrays, and recoverability-aware system design. Rather than treating manufacturing defects solely as yield loss, the work proposes a shift from physical yield optimization to functional yield optimization through architectural redundancy, defect mapping, adaptive routing, and software-level recovery. The manuscript further discusses the potential economic implications of this approach, including the possibility that higher physical defectivity may remain acceptable if functional recoverability is sufficiently high. This work is intended as a framework-level research contribution and conceptual foundation for future fabrication, benchmarking, and validation studies.