Institute of Microelectronics

A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout

Adder neural networks remove multiplication from convolution, yet their direct L1-distance datapath still requires subtraction, absolute-value generation, and wide accumulation. We address this cost by mapping the online L1 operation to minimum selection and time-domain accumulat...

A Design-Technology Co-Optimization Framework Based on Process-Parameter Sensitivity Analysis

This paper proposes a design-technology co-optimization (DTCO) framework applicable to advanced technology nodes, which accelerates the process optimization exploration for such nodes. Developing automatic parameter extraction algorithms tailored for the BSIM-CMG model, along wit...

Enhancing Dermatological Image Segmentation via In‐Sensor Computing With a Neuromorphic Ga‐Doped ZnO Nanorod‐Based Optoelectronic Memristors

ABSTRACT Conventional computing architectures with separate sensing and processing units are plagued by latency and energy inefficiencies. By fusing local data and computation, in‐sensor computing enables real‐time localized data processing and decision‐making, approaching the en...

Mechanistic Mapping of Additive Cracking for Hybrid SEI Construction in Aqueous Zinc‐Ion Batteries

ABSTRACT Electrolyte additives represent a promising strategy for regulating the solid‐electrolyte interphase (SEI) in aqueous zinc‐ion batteries. However, the underlying molecular mechanisms by which these additives mediate SEI formation remain insufficiently understood. Here, w...